The GBT-SerDes ASIC prototype

The GBT Project

The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planned for the SLHC, the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs address this issu...

Low cost, prototype ASIC and MCM fabrication and assembly from the MOSIS service

The MOSIS Service at the University of Southern California’s information Sciences Institute offers services to obtain custom designed, prototype quantities of ASICs and Multichip Modules (MCMs). The service recently added MIDAS, the MultiChip Module Designers’ Access Service for MCM fabrication to the list of standard oflerings. Thus a designer can now access domestic, high-volume IC and MCM pr...

A 3 mm Receiver for the GBT

Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation

In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze the differences between a prototypical FPGA implementation and standard cell realizations in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using the hardware description language VHDL, which offers the opportunity of adding special, optimized hardware blocks for variou...

The IBM ASIC/SoC

This paper describes the methodology employed by the IBM Microelectronics Division for the design of its Blue Logic applicationspecific integrated circuits (ASICs) and system-on-a-chip (SoC) designs. This methodology is used by both IBM ASIC and SoC designers, as well as OEM customers. A key focus of the IBM ASIC/SoC methodology, outlined in the first section of this paper, is the first-time-ri...